1. Field of the Invention
This invention relates generally to semiconductor gate device fabrication techniques, and particularly to a method and structure for forming multiple self-aligned gate stacks for logic devices and memory.
2. Description of Background
Structures in semiconductor devices such as logic gates may be fabricated on silicon wafers. The logic gates include stacks of materials that are aligned on the silicon wafers. The logic gates are formed, in part, using shallow trench isolation (STI). Existing methods for producing multiple logic gates do not allow a number of gates comprising different materials to be formed on the active regions of the silicon wafers or for the gate stacks to be self-aligned.
It is desirable to fabricate a self-aligned structure for semiconductor devices that may be easily etched, and that includes a number of gate stacks each comprising different types of materials.